An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA

Field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed. As most CNN accelerators focus on dense neural networks, to solve the problem of difficult hardware deployment due to irregular networks, we propose a method for sparse neural networks in our work. The storage and coding format of sparse data obtained by the block pruning method is designed to make it friendly to implement on FPGA. Besides, we also propose an efficient and simple data flow by the planarization of the whole convolution calculation process. The experimental result demonstrates that our implementation can achieve clock frequency of 190 MHz, power consumption of 13.32 W and inferencing speed of 16.37 ms. Compared with some typical Mobilenet implementation schemes, our method has been proven to achieve a better balance between frequency, accuracy, power consumption, and speed.