FPGA-Based Configurable and Highly Flexible PAM4 SerDes Simulation System

In this article, a configurable and highly flexible four-level pulse amplitude modulation (PAM4) serializer/deserializer (SerDes) simulation system based on a field-programmable gate array (FPGA) is designed, which can simulate all bit rates currently supported by actual chips, such as 112 Gb/s. Compared to software simulation systems, the efficiency of this hardware simulation system is greatly improved. This simulation system allows parameterized configuration, and when paired with a CPU, it can save simulation data from various stages. Therefore, this simulation system can help integrated circuit (IC) designers save time and resources, design SerDes chips under different channel conditions, explore the error model of SerDes chips, and design improved equalization and forward error correction (FEC) schemes. Because some existing SerDes module algorithms are not publicly accessible, the commonly used SerDes module algorithms are summarized in this article, and some of them are modified. First, a parallel architecture for a scrambler/descrambler is designed using the Chisel language, which can be used to construct synchronous or asynchronous scramblers/descramblers of any parallel stage. Second, for the designed simulation system, the sign-to-sign Mueller–Muller phase detector (MMPD) from nonreturn-to-zero (NRZ) to PAM4 is introduced, eliminating the detection of rising or falling edges and instead performing phase detection between any two unit intervals (UIs). Experiments on the designed simulation system show a maximum signal-to-noise ratio (SNR) error of 0.05151 dB compared to theoretical results under the same bit error rate (BER) condition and a mean error of 0.03488 dB. The simulation results agree with the theoretical prediction.