Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle

For high-resolution, high-accuracy applications, re-cent DPWM (digital PWM) researches use long DFF arrays, resulting in clock skew that may compromise DPWM performance. This study proposed a DPWM based on a matrix phase shifter and clock gating technique which only selects a specific row of DFFs during operation depending on the required level of $\mathrm{V}_{o}$. The proposed design minimizes the clock skew caused by redundant DFF array clock activity. In addition, it uses a single clock and does not need any extra signal for synchronization. It has a dead-time generator that prevents shoot-through. The proposed DPWM has been implemented in UMC 180-nm CMOS technology where an overall chip and core area of 1285 x 1285 $\mu \mathbf{m}^{2}$ and 725.1 x 282.8 $\mu \mathbf{m}^{2}$ are used, respectively. The all-PVT corner post-layout simulation confirmed the functionality of the design with a maximum duty cycle of 90.6% at $\mathbf{C}_{load}=60\ \text{pF}$ and $\mathbf{f}_{clk}=100$ MHz.