FPGA Implementation of High Speed Convolutional Encoder and Viterbi Decoder for Software Defined Radio

Attenuation, interference, noise, and distortion affect any wireless communication system's data transfer, making it more difficult for the receiver to receive precise data. Convolution encoder is used to fix errors at the receiver end. Software defined radio may adjust to different encoding and modulation schemes by changing its configuration. In this work, convolutional encoding with a 1/2 code rate and a 3 length constraint is proposed. The updated Viterbi decoder architecture optimizes the key route, enabling higher speeds. MATLAB is used for simulation to verify the Viterbi design. Verilog HDL for RTL coding and a Xilinx Spartan Series FPGA is used in the implementation. ModelSim and Vivado are used for functional and timings simulations.