Study on Voltage Influence on FPGA-Based Time-to-Digital Converters

Field programmable gate arrays (FPGAs) based time-to-digital converters (TDCs) have been broadly investigated and widely used in recent years. However, voltage variations on the power distribution network (PDN) of FPGA are significantly affecting and sometimes devastating to the TDC performance. In this paper, we experimentally measure the performance changes of the tapped delay line (TDL) based TDC under conditions that the PDN has static and transient voltage variations and analyze the voltage influences theoretically. The test results show 0.2%/mV degradation of the TDC resolution with voltage drop and 12%1mV deterioration of the average RMS precision with voltage deviation from typical. Besides, performance degradation due to transient voltage fluctuations caused by switching activities of adjacent digital circuits is also experimentally demonstrated. In particular, the RMS precision exhibits periodic deterioration with the measured time interval, which can be reasonably explained in theory. For the influence coming from static voltage variations, we find the performance change can be greatly suppressed by the dynamic calibration method. However, for the influence coming from voltage transients, the performance degradation is inevitable, which raises a warning for FPGA management, especially for multi-tenant FPGAs where multiple untrusting cloud users simultaneously reside in a single FPGA. The test results and theoretical analysis in this paper can guide system optimization and real-time correction to reduce the impact of voltage transients.