Engineering-Informed Design Space Reduction for PCB-Based Power Delivery Networks

An engineering-informed approach to reduce a feasible design space for printed circuit board (PCB)-based power delivery networks (PDNs) of high-speed digital systems, is proposed. A reduction in the sampling of a factor of three decades from more than
$1\times 10^{6}$
sampling points to
$1\times 10^{3}$
sampling points is achieved. This enables to generate data samples for training machine learning (ML) tools being applicable in the design process of the PDNs for a subset of the formerly defined design space. Reducing the complexity is performed by focusing on a specific problem namely a PCB with two via arrays and a fixed PCB size. First a data-driven sensitivity analysis of the different PCB design parameters is performed reducing the design space of parameter variations which show a very small impact on the PDN impedance. Second, a physics-informed and data-supported reduction of the PCB stackup is performed showing the possibility to cover a wide range of stackups with minimal stackup definition. All investigations are performed in the frequency range from
$\mathrm {1~ MHz}$
to
$\mathrm {1~ GHz}$
, relevant for investigations of the decoupling of PCB-based PDNs. Based on a developed PDN design flow, artificial neural networks (ANNs) are trained to predict key features of the electromagnetic (EM) behavior of the PDN. All generated data samples are provided in the SI/PI-database as Touchstone files (
https://www.tet.tuhh.de/en/si-pi-database
).