Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing

The impulse response has a finite period in a finite impulse response filter (FIR). In various applications of digital signal processing, a higher order FIR filter is necessary to achieve precise frequency specifications. However, the quantity of adders and multipliers rises linearly with the leading filter length. The multiplier block, adder block, and flip flop block are the core building blocks for the creation and application of the FIR filter. The multiplier, which is the adder's slowest block, has a significant impact on the FIR filter's performance. The use of the Booth Multiplier and carry select adder in the Finite Impulse Response Filter will reduce the delay. The filter and other filters have been compared for several parameters. The proposed lowpass filter, a 15-tap filter with Verilog HDL design and Xilinx 14.7 Vivado tools implementation, is proposed. There has been a reduction in both the area and the delay. Additionally, the booth multiplier has reduction in delay, lesser power consumption, and operational frequency which makes it an excellent choice for building FIR filters for low voltage and low power VLSI applications.