XNOR-XOR based Full Adder Using Double Pass Transistor Logic

The XNOR-XOR circuit is a vital part of several arithmetic circuits. An 8T full-adder circuit and a 4T XNOR-XOR circuit are presented in this study. Due to the proposed circuits, extremely low output capacitance and minimal short-circuit power dissipation, the power consumption and area are exceptionally low. To compare quantitatively and with fewer transistors, the proposed full adder is implemented at an elaborate transistor level. The proposed full adder design framework utilizes an optimized simultaneous XNOR-XOR circuit with double pass transistor logic. The design is simulated in Cadence Virtuoso using 45nm CMOS technology. The results highlight that the proposed design consumes less power and area compared to conventional methods with optimal design.