An Intelligent System With Reduced Readout Power and Lightweight CNN for Vision Applications

An always-on intelligent system comprising of an image sensor requires continuous functioning of each pixel. This includes sensing the illumination content of the scene and also the conversion of the analog values into their digital representations. Therefore, power consumption during analog to digital conversion and computational cost at the image sensor module become critical while designing a system that is always-on and incorporates intelligence near the sensor module. This work focuses on the inherent property of the ADC for converting the analog pixel values to digital values by taking a defined number of analog-to-digital converter (ADC) cycles. The design factors considered are 1) Power saving due to reduced ADC conversion cycles for each pixel; 2) The reduced bit-precision of the processing unit to reduce hardware cost; 3) The dataflow design through
hls4ml
, which produces parallel computational modes for low latency CNN architectures. The proposed work implements two lightweight CNN models with reduced parameters as compared to the original architectural models of VGG16 (like) and SqueezeNet (like) which are trained in Qkeras and deployed on Zynq UltraScale+ MPSoC board. In addition, the design pipeline is validated on the MobileNetV2 and GhostNet architectures to demonstrate its generalization ability. A detailed analysis shows that limiting the number of ADC bits from 8 to 4 reduces the mean accuracy merely from 50.3 to 49.17 for VGG16 (like) and 67.83 to 67.80 for SqueezeNet (like) model, however, the readout power is significantly reduced from 140.45 mW to 7.7 mW for STL-10 dataset with
$96\times96$
image resolution. Additional experiments are conducted with CIFAR-10 and mini-ImageNet datasets for classification and with Oxford-IIIT Pet Dataset for segmentation. The proposed work, thus, provides empirical evidence that a reasonable performance for intelligent vision tasks with power saving can be achieved by tuning CNN models to work with reduced ADC bit precision.