Cask HLS: A Better Development Tool for Vitis HLS

The increasing complexity of modern hardware designs makes it difficult for the developer to easily design, validate, and test ideas while creating RTL (Register Transfer Level) logic. HLS (High-Level Synthesis) has been introduced as a tool to easily design complex and specialized hardware such as machine learning accelerators, processors, and other FPGA designs on a behavioral level, significantly reducing the size and time typically necessary for such undertakings. However, the complex compilation process and the semantic gap between behavioral code and synthesized hardware make resulting designs hard to verify and debug. Cask HLS, a web-application debugger for Vitis HLS, not only loads relevant debugging information faster than Vitis, but also creates new visualizations and quality-of-life improvements such as a side-by-side C++/LLVM-IR schedule viewer, linter, and function call graph, allowing debugging through a lightweight, portable application.