FPGA-based Hardware Implementation of the ART-1 classifier

The paper is devoted to the problem of hardware implementation of a classifier built on the basis of adaptive resonance theory (ART). The paper presents a variant of the hardware implementation of the ART-I network, which processes bit input vectors and performs their classification into a certain number of clusters. The network architecture, the features of implementation of control modules, the structure of neural layers and rules of their interaction are shown. The simulation results confirm the operability of the classifier and its effectiveness. The developed classifier is a prototype for portable and low-power AI modules in hardware implementations of the Internet of Things.