Design and Implementation of Cordic based Digital Modulation Techniques using DPLL

This document delineates the implementation of Cordic based FPGA digital modulation techniques using DPLL for great-resolution digital communication applications. We are emphasizing upon digital phase lock loop-based Verilog-based code simulation for routinely adopted digital modulation techniques. In this work, based on the fundamental principles of sampling and quantization of DPLL digital signals, the sine wave which have been produced is smooth and plain in nature. Modelsim and Xilinx-ISE are used to run the simulation, which uses the VERILOG Hardware description language. A 32-bit serial data transmission system with self-adjusting carrier frequency and bit length has been developed.