Mechanisms of stress-induced voids in multi-level Cu interconnects

One of the most serious problems in Cu-based multilevel integration is the failure in stacked vias caused by stress-induced voids. In this paper, the failure mechanism of the stacked via resistance is evaluated by analyzing the effects of the conditions of deposition and annealing in electroplated-Cu (EP-Cu) and the damascene structure scheme in a 64-bit RISC microprocessor with 7 copper layers. The stress-induced void is closely related to the stress change and the volume shrinkage of EP-Cu generated during deposition and annealing. The stacked via failures can be effectively suppressed with the application of two-step deposition and annealing in the EP-Cu process at the relatively low temperature of about 200/spl deg/C and the single damascene scheme for the layer of Via-5/Metal-6.