A simulation method for predicting packaging mechanical reliability with low /spl kappa/ dielectrics

It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, a multi-level, multi-scale modeling technique is used to study the die attach process. Four-level models are built to analyze the packaging impact on the wafer-level behavior. An interface fracture mechanics-based approach is adopted to predict interface delamination. The impact of thin film residual stresses is studied at both the wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages are evaluated. Critical failure locations and interfaces are identified for both packages. Two solutions are suggested to prevent catastrophic delamination in copper low-k flip-chip packages.