CVD barriers for Cu with nanoporous ultra low-k: integration and reliability

The drive for greater integrated circuit performance has led to the need for faster interconnect systems, the development of porous ultra low-k dielectrics and thin CVD barriers. The porous structure and lower modulus of low-k dielectrics has made integration a greater challenge. In this paper, we report on an initial feasibility study on of a new spin-on nanoporous low-k dielectric with a CVD TiN(Si) barrier, for Cu dual damascene integration.