Investigation of BVdss instability in trench power MOSFET through DLTS, electrical characterization and TCAD simulations

In this paper, we investigated the drain to source breakdown voltage (BV
dss
) instability during avalanche current drain stress of Shielded Gate MOSFET (SG-MOSFET) structure and we propose a new methodology to correlate electrical results to TCAD simulations. The presence of positive charged states at the Field Plate (FP) oxide/Si interface was confirmed by Capacitance Deep Level Transient Spectroscopy (C-DLTS). Thus, it was implemented in TCAD simulations that predict the experimental behavior of two architectures. Thanks to these results, walk-in contributors were discriminated to suggest a pathway to increase device robustness with a slight Ron impact.