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HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling | IEEE Conference Publication | IEEE Xplore

HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling


Abstract:

Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In m...Show More

Abstract:

Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In many cases, the implementation of DyNNs can be sub-optimal due to its underlying backbone architecture being developed at the design stage independent of both: (i) potential support for dynamic computing, e.g. early exiting, and (ii) resource efficiency features of the underlying hardware, e.g., dynamic voltage and frequency scaling (DVFS). Addressing this, we present HADAS, a novel Hardware-Aware Dynamic Neural Architecture Search framework that realizes DyNN architectures whose backbone, early exiting features, and DVFS settings have been jointly optimized to maximize performance and resource efficiency. Our experiments using the CIFAR-100 dataset and a diverse set of edge computing platforms have shown that HADAS can elevate dynamic models' energy efficiency by up to 57% for the same level of accuracy scores. Our code is available at https://github.com/HalimaBouzidi/HADAS
Date of Conference: 17-19 April 2023
Date Added to IEEE Xplore: 02 June 2023
Print on Demand(PoD) ISBN:979-8-3503-9624-9

ISSN Information:

Conference Location: Antwerp, Belgium

Funding Agency:


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