Novel 32nm CMOS Ternary 3‘s Complement Generator

Present study unfolds a new optimized scalable circuit topology to generate the 3’s complement of a base-3 input and the corresponding 2-step design strategy with respect to an illustrative 4-trit 3’s complement generator is elaborated. A novel idea at step-l generates the 2’s complement of a ternary-input. Next, in step-2 the ternary ‘‘1’’ is added with the 2’s complement result from step-l in order to generate the 3’s complement output. The clever hardware optimization strategy applying possible fixed-input to the circuit (wherever applicable) is adopted here for the purpose. The complete 4-trit 3’s complement generator is designed on 32nm standard CMOS technology using BSIM4 model parameters with 0. 9V supply-rail at 27°C temperature using SEdit of Tanner EDA. The extensive T-Spice transient simulations with all possible test patterns validate the circuit operation. As per evaluation the proposed circuit produces output with S3.37ps propagation delay, 175.65$\mu$W averagepower and 14.64× 1$0^{-15}$J PDP when operated with 100MHz ternary input.