FIR Filter design using Urdhva Triyagbhyam based on Truncated Wallace and Dadda Multiplier as Basic Multiplication Unit

Image represents a two dimension signal which can be compressed to enable effective usage of channel bandwidth. Any image processing algorithm uses Low Pass Finite Impulse Response filters as basic operation. This paper focuses on the design of finite response filter based on Vedic mathematics for multipliers and Carry Look Ahead adders. To enable image compression, truncated Wallace and Dadda multipliers are used with an acceptable accuracy. The designs are modeled in Verilog HDL, verified in Quartus II Tool for Cyclone III FPGA. The results are evaluated for truncated Wallace and Dadda multipliers in comparison with basic Wallace and Dadda Multipliers and are further validated for FIR filters with 4,8,16 and 32 taps with 4, 8, 16 and 32 bit word processing capability. The truncated Dadda multiplier for 4x4 multiplier is less by atleast 3.4% and for remaining n-bit multipliers, truncated Wallace multiplier shows the minimum area occupied by atleast 4.86%, 6.73%, 7.11% and 6.63% for 8x8,16x16,32x32 and 64x64 bit multipliers respectively. The FIR Filter using truncated Wallace multiplier uses atleast 25% less area but FIR Filter using truncated Dadda multiplier uses on an average atleast 4% less delay. The variation in power dissipation is negligible but the maximum possible frequency is on an average improves by atleast 0.24% for truncated Dadda multiplier based FIR Filter. As the order of the filter increases, the area utilization increases, delay decreases with slight changes in power dissipation. Hence, the proposed designs prove to be best suited for image processing applications for a specified accuracy.