Performance Analysis of Non-overlapping Two Phase Clock Signal Generators

In this paper, the performance of three non- overlapping clock signal generators are analyzed and compared with each other. The first type of clock generator is based on combinational gates propagation delay and inversion of the signal. The second one is derived from master slave JK flip-flop along with NAND gates. The final type is extracted from a SR latch realized using NOR gates and inverters to induce delay. All the three clock generators are designed in 180 nm CMOS technology and simulated using SPICE tool. The various performance parameters such as under-lap, power consumption, driving capability and number of transistors are measured for all the types and tabulated for comparison. The performance analysis helps one to select the suitable topology for the given application.