Architecture Dependent Constraint-Aware RFET Based 1T-DRAM

The constraints of retention time (T
Ret
), speed, and power consumption at fixed total length (
$\mathrm{L}_{\text{Si}}=100\ \text{nm}$
) and minimum bias levels (4) present bottlenecks in the operation of reconfigurable transistor (RFET) as capacitorless (1T) dynamic random access memory (DRAM). A constraint-aware assessment of 1T-DRAM showcases potential for high
$\mathrm{T}_{\text{Ret}}=2.9\ \mathrm{s}$
with sense margin (SM) >
$25\ \mu\mathrm{A}/\mu\mathrm{m}$
and current ratio (CR) > 10
²
at 85°C. Scaled down 1T-DRAM with
$\mathrm{L}_{\text{Si}}=50\ \text{nm}$
exhibits a decent T
Ret
(∼35 ms) at write (4 ns) and read (5 ns) time with
$\text{SM}= 40\ \mu\mathrm{A}/\mu\mathrm{m}$
and
$\text{CR}=10^{3}$
which highlights prospects for embedded applications. Disturbance due to shared bit and word lines is also discussed.