A Smart System for Binary Image Denoising using DCNN on FPGA

Integrated circuits based on digital image processing have been increasingly important in recent years due to their usefulness in many different fields, including manufacturing, agriculture, remote sensing, and medicine. The development of low-area, low-power, and low-delay processors is a significant challenge. The majority of these efforts have targeted efficient noise removal filtering by minimizing the resources required to accomplish it. Existing filtering approaches require a lot of space, a lot of power, and a lot of time since noise is dynamic and distributed randomly throughout images. Finally, this research work is extended by incorporating QCA technology to reduce the space, power, and time needed to build an efficient filtering method with altered noise deviation features. This research study proposes a majority logic gates technology to create DCNN-based FBF on a field-programmable gate array (FPGA). By using the vast majority of logic gates to design the MCSA, considerable gains can be achieved in terms of speed, execution time, area, power, and latency over the RCA used in traditional CNN. The proposed DCNN-FBF is also used in the implementation of an image denoising application. The proposed methodology has been shown to improve hardware performance relative to state-of-the-art methodologies, as evidenced by both hardware and extensive simulation findings. In addition, as compared to traditional filtering methods, the proposed image denoising solution has achieved higher values of structural similarity (SSIM) and PSNR.