Demonstration of A 3D Chip by Logic-DRAM Stacked Using Paired TSV Interconnection through Interface for AI/Edge-Computing Application

A 3D chip by Logic-DRAM stacked was demonstrated by wafer on wafer (WoW) oxide bonding and paired through-silicon-via (TSV) in this work. The proposed paired TSV (Unit size < $20 \mu\mathrm{m}$) and interconnection network were used for interface interconnection of two stacked wafers. This work showed the proper TSV landing metal layer could reduce contact resistance of paired TSV up to 96%. Although the top Si substrate thickness was thinned down to $3\mu\mathrm{m}$, the 3D chip with paired TSV still sustained the key reliability tests of structural interconnection. The process robustness of the structure was checked by daisy chain with 17Kea of paired TSV (1E4/mm²). The Logic-DRAM system function of the 3D chip was also verified. The computing performance of the 3D chip projects increase 60∼80% than commercial product according to this architecture.