A 7∼10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit Using Automatic Band Selector

A 7∼10.5-Gb/s reference-less clock and data recovery (CDR) circuit is presented. By using the proposed frequency decremental circuit (FDC) and the automatic band selector, the frequency capture range of a CDR using a linear phase detector is extended. The FDC also dynamically controls the current of the charge pump to shorten the frequency acquisition time. This CDR circuit is fabricated in the 40-nm CMOS process and its active area is 0.102 mm². The power of the CDR circuit is 39.6mW. For a 10.5-Gb/s PRBS of 2¹⁵–1, the measured root-mean-square jitter of the deserialized-by-16 retimed data at 656.25Mbps is 5ps. The measured high-frequency jitter tolerance is 0.26 UIPP while the bit error rate is less than 10⁻¹².