A Simulation Study of Junctionless Forksheet on Sub-2 nm Node Logic Applications

This article presents an evaluation of the CMOS logic performance of a junctionless (JL) forksheet based on 3-D numerical simulation. The study investigates the transfer characteristics and gate capacitance of the JL-forksheet with channel doping ranging from
${1} \times {10}^{{19}}$
to
${6} \times {10}^{{19}}/\text {cm}^{{3}}$
, to determine the optimal performance of the device. Results show that due to its lower gate capacitance, the JL-forksheet has a lower intrinsic delay than the IM-forksheet. Moreover, the JL-forksheet demonstrates improved logic performance in terms of rise time, fall time, propagation delay, and maximum oscillation frequency, with improvements of at least 25%, 35%, 17%, and 21%, respectively, as compared to the IM-forksheet. Based on its simple fabrication process, better power efficiency, and improved digital logic performance at the sub-2 nm technology node (N2), the JL-forksheet exhibits strong potential as a high-performance CMOS logic solution in the post-Moore era.