Reconfigurable Hardware Implementation of CNN Architecture using Zerobypass Multiplier

The current state-of-the-art in image recognition, segmentation, and localization algorithms has reached an extremely high level of accuracy thanks to the development of deep neural networks and their use in computer vision problems. Specifically, Convolutional Neural Networks (CNNs) have reached human-level performance in image classification and detection. CNN must be executed on a portable, low-cost, and low-power-consuming device for the object classification/detection use cases. However, real-time execution of CNN based applications is hindered by these devices’ limited computing resources and low on-board memory storage capability. In this dissertation, we introduce hardware-efficient algorithms for performing complex computations in CNN at low cost and with minimal power consumption. Additionally, we provide efficient VLSI architectures based on systolic arrays for creating high-performance devices for running CNN.The limitations of traditional CNN for detecting occluded objects are also outlined in this thesis. We propose an improved CNN with self-feedback layers and present an algorithm to increase the detection accuracy of the hidden objects. Improved accuracy in detecting hidden objects is found when the enhanced CNN is compared to the gold standard dataset. In addition, enhanced CNN requires a much larger number of computations to execute than regular CNN. We introduce a low-cost, low-power VLSI architecture design for efficient hardware execution of improved CNN.