Goertzel Algorithm Design on Field Programmable Gate Arrays For Implementing Electric Power Measurement

The Goertzel algorithm has a role in signaling to determine the modulus and phase of the harmonic components. This algorithm has the advantage of the Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) algorithms in some cases of harmonics. Moreover, Goertzel’s algorithm allows it to be used for signaling whose frequencies are not multiples of integers. This paper aims to design the hardware design of the Goertzel Algorithm by displaying register transfer logic (RTL), routing speed optimization, and component consumption of Field Programmable Gate Array (FPGA) resources. The FPGA type used in the design of this algorithm uses the SPARTAN-3E XC3S500E-4-FG320 evaluation board. The FPGA design from this algorithm is then applied to electric power measurement instrumentation. Hardware programming on this FPGA utilizes the Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language, which is often referred to as VHDL. The results of consuming the components used in the FPGA for this design use 191 slices, 185 slice flip-flops, 356 of 4 inputs look-up table (LUT), 14 Input/Output (I/O), 14 Bonded I/O, 1 Multiplier MULT18X18SIO, and 1 Global Clock (GCLK). Meanwhile, the routing optimization speed of this FPGA model has a delay time of 7.693 ns or, in other words, it showed a maximum frequency of 129.988 MHz.