Tunnel FET based Standard Logic Cell Implementation: A Circuit Perspective

Tunnel FETs can be endorsed as a potential successor of bulk Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology owing to Complementary-Metal-Oxide-Semiconductor (CMOS) compatible fabrication and improved OFF current characteristics. They may be the best fit for next generation sensing and low power computing applications which involve mostly random sparse triggering events. This paper provides a compact overview of the circuit design prospects of Tunnel FETs. Several techniques to overcome the basic logic cell implementation challenges have been discussed. These include an all n-type Tunnel FET (TFET) logic and a novel hybrid logic design style. An analysis showing the impact of these techniques on the performance and reliability of the fundamental logic blocks like inverter and NAND gates has also been presented.