Design and Implementation of a FIX Protocol Offload Engine for SET Market Data

This paper presents the design of a FIX protocol offload engine for SET market data processing. To achieve low latency, parallel and pipelining concepts are utilized wherever possible. Our design is implemented through VHDL code on an Intel MAX10 board at 125-MHz based clock with 1 GbE network. The results show that the Rx module can achieve a maximum decoding latency of $4.032\ \mu\mathrm{s}$ and a constant processing delay of 26 clock cycles after a FIX market data was received while the Tx module achieves a maximum latency of $3.98\ \mu\mathrm{s}$ for generating a FIX market data request. Moreover, the $T$ x/Rx module has an ability to encode/decode 8-digit ASCII values. The latency of the design can be further improved using a higher data width or greater gigabit ethernet environment.