FPGA Based Register Access and Memory Control for 5G Beamforming Processing

The Evolution of radio communication during the last decades has brought major improvements in exploring new types of architecture and technologies to meet the growing demands of the consumer. A fifth generation (5G) network, actively standardized by 3^rd Generation Partnership Project (3GPP) under Release 15, exploits the millimeter wave frequencies to dramatically increase the network bandwidth. Besides continuous improvements in terms of data capacity, a technique called beamforming is brought up which is a distinguishable feature from the previous generations. In the current approach, we design 4 Transmitter & 8 Receiver (4T8R) macro-O-RAN Radio Unit (O-RU) to implement beamforming which extracts the beam weights generated by O-RAN Distributed Unit (O-DU) and sent via C-plane packets, and the address calculation to store the beam weights is calculated with respect to the beam ID. O-RU needs to fetch the beam weights associated with that beam ID from the internal memory. The beam ID serves as a pointer to read from beam weight memory and performs complex multiplication and addition of those to indicate which beam to be applied for further processing. The proposed design is carried out using Verilog HDL and the design is tested on Xilinx Zynq UltraScale+ MPSoC that demonstrates the implementation which achieves high gain beam intended for the specific user.