Intuitive Probabilistic Conditional Approach in LDPC for Memory Corrections

The implication of power, area and delay have been the critical aspects of the design elements on any application chosen. With different application interests in the design features with NOC, CNN other machine learning features have created a revolutionary model on AI features of Chips which inculcate the Algorithms with Less power capabilities. Though these implementations have been the prominent design still faces memory errors and data redundancy. One such features of design on low power consumption with parity check models are implemented on LDPC and Turbo codes for wireless systems. The proposed BCS model with improved probabilistic cumulative approach with machine learning feature have improvised the different possible changes in power relative on input requirement and output dissipation. The proposed model with low power feature and analysis on Machine learning algorithms approach with clock gating model have effective reduced the power from 3.2Watts to 0.145W. The tabulated values for power on input features and output dissipated are represented with existing LDPC's.