Functional Verification of SPI Protocol using UVM based on AMBA Architecture for Flash Memory Applications

Effective verification of circuit designs is required because integrated circuit designs keep growing, and hence the process of verification is becoming major challenging and prolonging action. Hence, there is a need for a robust testbench hierarchy that contains essential common control components which are widely transformable and can be simply extended to models. One architecture that implements architectures for testbench in verification environments along coverage with CRT is the Hierarchy of Universal Verification Methodology (UVM) (Limited Random Test). According to the verification strategy developed following a thorough analysis of the SPI protocol specifications, the current work is appropriately focused on the SPI Single Master and Multiple Slave protocol based on UVM verification. The UVM test bench targets on bringing forth random vectors that are fed to a DUT (Design Under Test) or SPI module and compares them with the output secured by a scoreboard. This procedure helps to validate SPI functionality. The SPI interface has flexible bandwidth and frequency and can give and take data from multiple slaves and powerful APB SPI controllers. An SPI device is difficult to manage over the AMBA bus because it is usually attached to the main data bus of the system, such as the AMBA APB bus interface core. In the field of embedded systems, flash memory has gained its significance. This paper describes how an analog FPGA-based SPI FLASH memory system can be used in various applications by taking advantage of its features such as parallelism, reconfiguration, fast real-time and high speed.