An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS

A low-power, small-area, and medium-to-high-resolution ADC is one of the critical building blocks in an SoC. lt is also a primary bottleneck of SoC time-to-market due to ful.lcustom design. The $\mathrm{p}_{\mathrm{i}}$ rior work of [1] addressed this issue by synthesizing a MASH ADC using augmented analog customized blocks. Although the design productivity is increased, the ADC performance is sacrificed, leading to only 58. 9dB SFDR and 9. 5b ENOB. Besides, the highly customized blocks such as opamp and comparator greatly restrict the design flexibility. An automated SAR ADC design by taking advantage of its inherent digital-friendliness is demonstrated in [2] –[4]. Nonetheless, the performance of these 3 works is still limited to 9. 5b ENOB. Also, a dedicated custom-made CDAC layout tool is demanded on top of the standard digital EDA tool, equivalently transferring circuit design effort to software development. A synthesized VCO-based $\Delta\Sigma$ ADC is proposed in [5]. However, this synthesis methodology cannot achieve high resolution due to the poor matching by automatic place and route (APR) and the low quantizer resolution. So far, none of prior synthesized ADCs has demonstrated over 69dB SNDR nor 75dB SFDR. Also, none of existing methodologies demonstrated synthesized ADCs for multiple specifications using one universal library.