Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits

Side channel analysis (SCA) is a low time-complexity technique of extracting secret information from a cryptographic 1C, which calls for low-overhead generic resilience techniques. While architectural and logical countermeasures [1] are explored widely, recently generic circuit-level countermeasures (e.g. voltage regulators [2] –[4], power balancing [5] or through a switched capacitor current equalizer [6], using an on-chip machine learning model [7], [8], and signature attenuation [9], [10]) have gained prominence due to low overheads and being architecture agnostic. Typical digital cryptographic core has two controllable ports, i.e., supply and clock. Most of the circuitlevel/physical layer countermeasures have primarily utilized the power port to reduce the side-channel leakage signal-to-noise ratio (SNR). Related to the clocking port, well-studied system-level clock frequency randomization techniques have been deemed ineffective with post-processing. However, the impact of circuit-level changes in the clocking circuitry and its device-circuit-system level interactions with inherent propeities of digital circuits and its impact on SCA leakage remains unexplored. Another key requirement for the countermeasure is to make it fully synthesizable for scalability across different technology nodes. This work, for the first time, exploits the inherent variability of CMOS digital circuits by providing a controlled slewed clock and demonstrates an extremely low-overhead technique for immunity against power and EM SCA, which can be easily combined with any of the supply port countermeasures for multiplicative effect on SCA resilience.