A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC

The smart edge nodes require efficient matrix-vector multiplications for local deep neural network (DNN) inference. Benefiting from its high density and CMOS compatibility, the eDRAM-based computing-in-memory (CIM) [1] –[4], especially with multi-level cells (MLCs) [4], attracts rising attention. However, the performance of prior MLCeDRAM CIM is severely limited by the inconsistency of weight representations during the programming and computing: weights are programmed as fixed voltages while transistor currents are used for computation. Thus, the programming of MLCs requires calibration due to the nonlinear transistor I-V, which can be extremely complicated in the presence of $V_{T H}$ variations. Furthermore, the computing precision is severely degraded by $\mathrm{V}_{\mathrm{TH}}$ variations when small computing currents are used for high parallelism. To fundamentally surmolunt this dilemma, we propose the first currentprogramming eDRAM CIM that unifies the weight programming and computing in the current domain. The enabling technique is a novel 3T1C eDRAM cell (Fig. 1, top right). It confers several key merits: 1) the cell is programmed by the weight current directly with the selfcalibrated voltage generated on the storage capacitor; it essentially stores the weight current instead of a fixed voltage, thus mitigating $V_{\text {TH}}$ variation and nonlinear transistor I-V impacts; 2) a dynamiccascoded read structure is proposed to significantly reduce the V
B
sensitivity while not requiring any bias voltage; 3) thanks to the accurately programmed cell, it supports MLC operation (8 current levels) without any calibration, largely increasing density; 4) a voltage-current two-step programming scheme significantly boosts the sub- $\mu \mathrm{A}$ current-weight writing speed. Combining these merits, the proposed eDRAM cell is naturally immune to transistor-level nonidealities, thus allowing a small LSB weight current of only 100nA. A $4 \mathrm{~b}$ CIM cell composed of 2MLCs is developed to support 4bsigned weights. It contains 15 current levels ranging from -700nA to 700nA. Fabricated in a $65 \mathrm{~nm}$ CMOS, the prototype achieves the highest macro-level 4b-MAC energy efficiency of 233-305TOPS/W among eDRAM CIMs.