ESD Behavior of Fin based Tunnel FETs

This paper investigates the reliability of a novel Fin-enabled vertical or area-scaled tunnelling FET proposed for sub-10-nm channel length operation. This device enables a smooth transition from FinFET technology to Fin-based vertical TFETs, while enjoying the benefits of FinFET architecture. To make this device commercial, it's important to understand the reliability performance of this device. This work explores the reliability physics of this device with detailed physical insight into the device operation and failure under ESD stress conditions. The proposed device has a deep N+ implant underneath the P+ source for the ESD protection applications, which has resulted in twice improvement in ESD failure current with less area overhead. The proposed concept can also be extended to the different class of tunnelFETs like Vertical/Area Scaled TFETs. The impact of various technology(SOI and Bulk) and device design parameters on the ESD behavior and robustness of Fin based TFETs is discussed. This has helped developing guidelines to design ESD robust or efficient protection concepts.