A RISC-V System-on-Chip Based on Dual-core Isolation for Smart Grid Security

With the development of digital power grids, the large number but low security level of smart power terminals makes the grid easier to face safe risks. In such a context, based on the protection needs of grid terminals, a secure System-on-Chip(SoC) architecture based on the RISC-V processor is proposed, which features dual-core isolation according to the hardware isolation principle and a secure boot based on the chain of trust. A secure serial port is also provided for digital authentication. The implementation of the architecture on FPGA shows that the influence of secure elements on the transmission is minimal.