SWaP Reduction for Optical Crosslink Modem Using FPGA SERDES

High speed optical communication is an important tool to increase communication bandwidth, especially as space-based payloads become more advanced and produce ever-increasing data volumes. There is significant interest in reducing SWaP in order to fly lasercom terminals on smallsats and cube-sats. A baseline, 2U payload for a LEO optical communications cubesat crosslink is presented consuming a total of 30W, half of which is from the 15W modem. This modem digitizes a photodetector output using a high-speed multi-bit A/D converter. Given the similarity of the OOK electrical waveform to the Ethernet physical layer standards for which FPGA SERDES are typically designed, there exists strong potential for replacing the multi-bit A/D converter with the GTX IP integrated into 7-series Xilinx FPGAs. Initial comparisons to a multi-bit approach are promising, with significantly reduced circuit board complexity and approximately 5.5W lower power consumption (43% modem power savings) at comparable bit error rates. Partial schematics and part recommendations are provided for board designers. SERDES configuration recommendations specifically targeting the 7-series GTX are also provided for a design performing clock and data recovery in the FPGA fabric. Finally, limitations and applicability to other FPGA families and vendors is presented.