1.1-GDI/s transmission between pausible clock domains

Asynchronous across-chip communication is increasingly attractive as clock distribution is becoming increasingly difficult at smaller feature sizes. Several globally asynchronous locally synchronous architectures (GALS), proposed recently, use handshaking protocols for across-chip communication. In this paper, we design two circuits that interface synchronous modules using pausible clocks to an asynchronous communication environment that uses single-track handshaking, a protocol shown to support high-speed asynchronous logic. The resulting circuits allow data transfer rates of up to 1.1 GigaDataItems/second, significantly higher than previous designs.