Electro-Thermal Characteristics of Junctionless Nanowire Gate-All-Around Transistors Using Compact Thermal Conductivity Model

The electrothermal performance of a junctionless nanowire [JL-nanowire (NW)] gate-all-around (GAA) transistors under self-heating effect (SHE) is examined for sub-5 nm technology nodes. These devices are generally fabricated on silicon-on-insulator (SOI) wafers, in which the thin active device layer confines silicon thermal conductivity (
$\kappa {)}$
and provokes SHE in the device. In this work, we proposed and upgraded the early reported compact thermal conductivity model (C-TCM) by considering the phosphorus doping effect for SHE analysis with any combination of doping, such as phosphorus/boron and arsenic/boron doping, which is validated with reported experimental data. The C-TCM is also compared with the existing Sentaurus TCAD Connelly thermal conductivity model (CN-TCM). The CN-TCM is only valid for undoped conditions at room temperature. This work shows that C-TCM can be used to simulate the realistic thermal behavior of the device with ambient temperature (
${T}_{A}{)}$
variation. With C-TCM, the nonuniform lattice temperature (
${T}_{L}{)}$
and heat generation were observed along the channel length due to the non-uniformity
$\kappa $
of the device. The influence of SHE on the device performance in terms of electrical characteristics and hot-carrier injection (HCI) is also observed along with
${T}_{A}$
variation. SHE rises the peak of
${T}_{L}{,}$
causing
$\sim $
10% ON-current and
$\sim $
0.7% mobility degradation. The SHE implication on HCI is also examined, and it was found that gate leakage current (
${I}_{\text {G}}{)}$
is enhanced by a factor of
$\sim $
55, highlighting the importance of thermal study for next-generation high-performance devices that do not compromise reliability.