Self-timed Fused Multiplier-Adder Pipeline Optimization

Self-timed circuits are optimal for implementing computing systems operating under extreme conditions. They function reliably under any changes in environmental and power conditions, detect all constant faults, and are more resistant to soft errors than synchronous counterparts. The article considers the problem of correct practical self-timed implementation of the operation of multiplying two operands with subsequent third operand addition and subtraction without intermediate product rounding as a pipeline with multiplexing of its parallel sections. Statistical analysis shows that in 64% of cases the operation result does not depend on the product, and in 29% of cases it does not depend on the third operand, which allows not performing a number of intermediate data transformations. Branching the pipeline reduces power consumption and improves its performance with the appropriate values of the input operands due to the lower complexity of the alternative path's stages. An active path marker FIFO (First Input First Output) guarantees the correct sequence of the operation results. The program ASPECT, analyzing circuits for semi-modularity, proves the self-timing of the described implementation.