A 2 Gb/s 256*256 CMOS crossbar switch fabric core design using pipelined MUX

In this paper, we present the design of a full-custom 2 Gb/s 256*256 crossbar switch fabric core circuit, using TSMC 0.25 /spl mu/m CMOS technology. To cope with the high data link rate, conventional approaches use duplicated multiple bit-slices of the switch core to reduce the core delay requirement. However, this increases the area and limits the size of the crossbar switch. To cater for a large number of input and output ports of the switch, we propose a novel 3-stage pipelined MUX-tree based architecture. As a result, the problem of designing a 256*256 crossbar is reduced to a 128*128 sub-crossbar. The clock cycle time of the switch core can be reduced below Ins. To achieve a 2 Gb/s link rate, only two bit-slices are needed instead of 4 or 8 in the conventional designs. By doing so, we can put a 256*256 crossbar on a single chip. The layout of the 128*128 sub-crossbar was designed and simulated. Experimental results show that 1 GHz clock frequency can be achieved. Furthermore, a full 2 Gb/s 64*64 crossbar switch digital core circuit was designed to demonstrate the whole pipeline structure. The area of this core is only 2.4 mm*1.9 mm and the power consumption is about 2.5 W at 1 GHz.