A low-voltage low-power fast-settling operational amplifier for use in high-speed high-resolution pipelined A/D converters

The most power-hungry circuit in a high-speed high-resolution pipelined analog-to-digital converter is the first stage opamp. In this paper a 1.5 V two-stage opamp is proposed which uses the cascode compensation to achieve a bandwidth higher than the miller compensation and also a class-A/AB output stage to reduce the high current needed in the opamp second stage to satisfy the slew-rate performance. HSPICE simulations show that considerable power is saved merging these two techniques in a 0.25 /spl mu/m CMOS process.