A square-root domain differentiator

In this paper, a square-root domain differentiator circuit is proposed for the first time in the literature. The implementation is based on an appropriate input stage that converts the input current into a compressed voltage at the capacitor's node and also senses the corresponding capacitor's current. The overall configuration of the differentiator is also constructed from geometric-mean and multiplier blocks. Simulation results confirm the correct operation of the proposed circuit.