A Concurrent Dual-band Differential CMOS Low-Noise Amplifier for Ku- and K-band Applications

This paper presents a 17/24-GHz concurrent dual-band low-noise amplifier (DBLNA) implemented in 130-nm CMOS technology. The proposed DBLNA is designed using fully differential structure and transformer-based balun is used at input and output ports for the conversion between single-ended and differential signals. The first-stage of the DBLNA employs the differential common source (CS) topology for the improvement of noise figure. The current reuse technique is used in the second-stage to reduce power dissipation and attain high gain simultaneously. Both stages adopt neutralized capacitors to enhance the stability of the DBLNA. The DBLNA exhibits the same simulated peak gains of 13.6 dB at 17 and 24.6 GHz respectively. The simulated noise figures are 5.0/4.2 dB at 18.5/24.6 GHz. Both the input and output return losses are below −10 dB from 17 GHz to 30 GHz. The simulated third-order input intercept points (IIP
3
) are 1.2/2.6 dBm at 17/24 GHz. The chip size of the concurrent DBLNA is 1.03×0.7 mm
²
with power consumption of 52.8 mW.