Full current-mode techniques for high-speed CMOS SRAMs

This paper describes an experimental 32 K/spl times/8 CMOS SRAM with a 9 ns access time at a supply voltage of 3 V using a 0.35 /spl mu/m 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28 mA at 100 MHz under typical conditions.