Implementation of an Energy Efficient Flip Flop by using Kintex, Virtex and Genesys FPGA Families

Several countries throughout the world are dealing with energy crises. To promote sustainable communication, an energy efficient JK Flip Flop has been implemented by using Vivado software and various FPGA families. Three alternative FPGA families of 7 series, such as Kintex, Virtex, and Genesys are used to determine the most power efficient series. Kintex, Virtex, and Genesys families utilize 0.996-Watt, 3.53 Watt, and 0.808 Watt of power, respectively. Based on the power efficiency, Genesys family of 7 series reduce power dissipation in contrast to the other two families. The energy efficiency of Genesys is beneficial to other FPGA families.