Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability

This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks. By introducing nonlinear operations through exploiting the random interconnections of delay stages, the proposed OIPUF can theoretically improve the physical unclonable function (PUF) security while consuming the same hardware resources as the conventional XOR arbiter PUF (XOR APUF). We further propose the metastability-detection (MD) arbiter to effectively improve the PUF reliability. Implemented on Xilinx Artix-7 field-programmable gate array, both the proposed (64,4)- and (64,8)-OIPUF demonstrate a good reliability and uniformity, with the proposed (64,8)-OIPUF showing a better uniqueness and strict avalanche criterion (SAC) performance. Measurement results also show that the proposed MD arbiter can reduce the bit error rate (BER) of the (64,4)- and (64,8)-OIPUF by
$\geq 68\times $
and
$\geq 48\times $
at up to 100 °C, respectively. Evaluated using the logistic regression (LR), artificial neural network (ANN), and covariance matrix adaptation-evolution strategy (CMA-ES) machine learning (ML) algorithms, the proposed (64,4)- and (64,8)-OIPUF can achieve a worst case prediction accuracy of 61.47% and 50.59% with up to 10M challenge–response pairs as training set, respectively, demonstrating a significant improvement over similar prior arts.