Failure Analysis of Sintered Layers in Power Modules Using Laser Lock-in Thermography

This research focuses on the application of lock-in thermography (LIT) for inspecting sintered chip interconnections, which are commonly used in electronic components. By utilizing laser LIT technology, this study showcases the ability of LIT to detect delamination in the sintered layer between copper pad and SiC chip, without the need for spray coating. The proposed LIT system offers an efficient solution for failure analysis (FA) of industrial electronic components that have thin layers, low emissivity surfaces, and high thermal conductivity, which often produce thermal failure contrast even below the noise level of infrared (IR) camera systems. The findings of this study highlight the potential of LIT technology for industrial inspections of electronic components and offer an alternative to existing inspection methods.