A 3.3 V 1 GHz high speed pipelined Booth multiplier

In this paper, a new MBE (modified Booth encoding) encoder, and a new MBE decoder are proposed at the CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of a critical path by levelling the complex gate in the MBE decoder. As a result, the MBE decoder is never the speed bottleneck of a pipelined Booth multiplier, and the speed of the MBE decoder can be improved up to 66.3 percent. Finally, a low voltage, high speed pipelined glitch-free Booth multiplier architecture is presented at 1 GHz in a TSMC 0.35 /spl mu/m process with a power consumption of only 100.52 mW.